Epson S1D13706 - Table 4-8: Summary of Power-On;Reset Options; Summary of Configuration Options

Epson Research and Development
Page 29
Vancouver Design Center
Hardware Functional Specification S1D13706
Issue Date: 01/11/13 X31B-A-001-08
4.5 Summary of Configuration Options
These pins are used for configuration of the S1D13706 and must be connected directly to
NIOV
DD
or V
SS
. The state of CNF[6:0] is latched on the rising edge of RESET#. Changing
state at any other time has no effect.
Table 4-8: Summary of Power-On/Reset Options
S1D13706
Configuration
Input
Power-On/Reset State
1 (connected to NIOV
DD
) 0 (Connected to V
SS
)
CNF4,CNF[2:0]
Select host bus interface as follows:
CNF4 CNF2 CNF1 CNF0 Host Bus
1000 SH-4/SH-3 interface, Big Endian
0000 SH-4/SH-3 interface, Little Endian
1001 MC68K #1, Big Endian
0001 Reserved
1010 MC68K #2, Big Endian
0010 Reserved
1011 Generic #1, Big Endian
0011 Generic #1, Little Endian
1100 Reserved
0100 Generic #2, Little Endian
1101 REDCAP2, Big Endian
0101 Reserved
1110 DragonBall (MC68EZ328/MC68VZ328), Big Endian
0110 Reserved
X111 Reserved
Note: The host bus interface is 16-bit only.
CNF3 Configure GPIO pins as inputs at power-on
Configure GPIO pins as outputs at power-on (for use
by HR-TFT/D-TFD when selected)
CNF5 WAIT# is active high WAIT# is active low
CNF[7:6]
CLKI to BCLK divide select:
CNF7 CNF6 CLKI to BCLK Divide Ratio
00 1 : 1
01 2 : 1
10 3 : 1
11 4 : 1