Epson S1D13706 - Host Bus Interface Signal Descriptions

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Epson Research and Development
Vancouver Design Center
S1D13706 Interfacing to the Intel StrongARM SA-1110 Microprocessor
X31B-G-019-02 Issue Date: 02/06/26
3.2 Host Bus Interface Signal Descriptions
The S1D13706 Generic #2 Host Bus Interface requires the following signals.
• CLKI is a clock input which is required by the S1D13706 Host Bus Interface as a source
for its internal bus and memory clocks. This clock is typically driven by the host CPU
system clock. For this example, it is driven by one of the SA-1110 signals SDCLK1 or
SDCLK2 (The example implementation in this document uses SDCLK2). For further
information, see Section 4.3, “StrongARM SA-1110 Register Configuration” on page
15.
• The address inputs AB[16:1], and the data bus DB[15:0], connect directly to the SA-
1110 address bus (A[16:1]) and data bus (D[15:0]), respectively. CNF4 must be set to
select little endian mode.
• AB0 connects to nCAS0 (the low byte enable signal from the SA-1110) which in
conjunction with the high byte enable signal allows byte steering of read and write oper-
ations.
• M/R# (memory/register) selects between memory or register accesses. This signal may
be connected to an address line, allowing system address A17 to be connected to the
M/R# line.
• Chip Select (CS#) must be driven low by nCSx (where x is the SA-1110 chip select
used) whenever the S1D13706 is accessed by the SA-1110.
• WE1# connects to nCAS1 (the high byte enable signal from the SA-1110) which in
conjunction with the low byte enable signal allows byte steering of read and write oper-
ations.
• WE0# connects to nWE (the write enable signal from the SA-1110) and must be driven
low when the SA-1110 is writing data to the S1D13706.
• RD# connects to nOE (the read enable signal from the SA-1110) and must be driven low
when the SA-1110 is reading data from the S1D13706.
• WAIT# connects to RDY and is a signal output from the S1D13706 that indicates the
SA-1110 must wait until data is ready (read cycle) or accepted (write cycle) on the host
bus. Since SA-1110 accesses to the S1D13706 may occur asynchronously to the display
update, it is possible that contention may occur in accessing the S1D13706 internal
registers and/or display buffer. The WAIT# line resolves these contentions by forcing
the host to wait until the resource arbitration is complete.
• The Bus Start (BS#) and RD/WR# signals are not used for this Host Bus Interface and
should be tied high (connected to V
DD
).
• The RESET# (active low) input of the S1D13706 may be connected to the system
RESET.