Epson S1D13706 - Table 6-10: Motorola MC68 K #2 Interface Timing

Epson Research and Development
Page 47
Vancouver Design Center
Hardware Functional Specification S1D13706
Issue Date: 01/11/13 X31B-A-001-08
1. t17 is the delay from when data is placed on the bus until the data is latched into the write buffer.
Table 6-10: Motorola MC68K #2 Interface Timing
Symbol Parameter
2.0V 3.3V
Unit
MinMaxMinMax
f
CLK
Bus Clock frequency 20 50 MHz
T
CLK
Bus Clock period 1/f
CLK
1/f
CLK
ns
t1 Clock pulse width high 22.5 9 ns
t2 Clock pulse width low 22.5 9 ns
t3
A[16:0], SIZ[1:0], M/R# setup to first CLK rising edge where
CS# = 0, AS# = 0, DS# = 0
11ns
t4 A[16:0], SIZ[1:0], M/R# hold from AS# rising edge 0 0 ns
t5 CS# setup to CLK rising edge 0 1 ns
t6 CS# hold from AS# rising edge 0 0 ns
t7a AS# asserted for MCLK = BCLK 8 8 T
CLK
t7b AS# asserted for MCLK = BCLK
÷
21111T
CLK
t7c AS# asserted for MCLK = BCLK
÷
31313T
CLK
t7d AS# asserted for MCLK = BCLK
÷
41818T
CLK
t8 AS# falling edge to CLK rising edge 1 1 ns
t9 AS# rising edge to CLK rising edge 1 3 ns
t10 DS# falling edge to CLK rising edge 1 1 ns
t11 DS# setup to CLK rising edge 1 3 ns
t12 First CLK where AS# = 1 to DSACK1# high impedance 5 40 3 14 ns
t13
R/W# setup to CLK rising edge before all CS# = 0, AS# = 0, and
DS# = 0
11ns
t14 R/W# hold from AS# rising edge 0 0 ns
t15 AS# = 0 and CS# = 0 to DSACK1# rising edge 4 23 3 14 ns
t16 AS# rising edge to DSACK1# rising edge 6 39 4 17 ns
t17
D[31:16] valid to third CLK rising edge where CS# = 0, AS# = 0,
and DS# = 0 (write cycle) (see note 1)
10ns
t18 D[31:16] hold from falling edge of DSACK1# (write cycle) 0 0 ns
t19 DS# falling edge to D[31:16] driven (read cycle) 4 32 3 14 ns
t20 DSACK1# falling edge to D[31:16] valid (read cycle) 0 2 ns
t21 DS# rising edge to D[31:16] invalid/high impedance (read cycle) 5 36 3 13 ns