Epson S1D13706 - Figure 6-11: Passive;Tft Power-On Sequence Timing; LCD Power Sequencing; Table 6-14: Passive;Tft Power-On Sequence Timing

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Epson Research and Development
Vancouver Design Center
S1D13706 Hardware Functional Specification
X31B-A-001-08 Issue Date: 01/11/13
6.3 LCD Power Sequencing
6.3.1 Passive/TFT Power-On Sequence
Figure 6-11: Passive/TFT Power-On Sequence Timing
1. t1 is controlled by software and must be determined from the bias power supply delay requirements of the panel
connected.
Note
For HR-TFT Power-On/Off sequence information, see Connecting to the Sharp
HR-TFT Panels, document number X31B-G-011-xx.
For D-TFD Power-On/Off sequence information, see Connecting to the Epson D-TFD
Panels, document number X31B-G-012-xx.
Table 6-14: Passive/TFT Power-On Sequence Timing
Symbol Parameter Min Max Units
t1
LCD signals active to LCD bias active
Note 1 Note 1
t2
Power Save Mode disabled to LCD signals active
020ns
LCD Signals***
GPO*
Power Save
t1
*It is recommended to use the general purpose output pin GPO to control the LCD bias power.
t2
**The LCD power-on sequence is activated by programming the Power Save Mode Enable bit (REG[A0h] bit 0) to 0.
***LCD Signals include: FPDAT[17:0], FPSHIFT, FPLINE, FPFRAME, and DRDY.
(REG[A0h] bit 0)
Mode Enable**