Epson S1D13706 - 3 S1 D13706 Host Bus Interface; Host Bus Interface Pin Mapping

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Epson Research and Development
Vancouver Design Center
S1D13706 Interfacing to the NEC VR4181A™ Microprocessor
X31B-G-008-02 Issue Date: 01/02/23
3 S1D13706 Host Bus Interface
The S1D13706 directly supports multiple processors. The S1D13706 implements a 16-bit
Generic #2 Host Bus Interface which is most suitable for direct connection to the NEC
VR4181A microprocessor. Generic #2 supports an external Chip Select, shared Read/Write
Enable for high byte, and individual Read/Write Enable for low byte.
The Generic #2 Host Bus Interface is selected by the S1D13706 on the rising edge of
RESET#. After RESET# is released, the bus interface signals assume their selected config-
uration. For details on the S1D13706 configuration, see Section 4.2, “S1D13706 Hardware
Configuration” on page 13.
3.1 Host Bus Interface Pin Mapping
The following table shows the functions of each Host Bus Interface signal.
Table 3-1: Host Bus Interface Pin Mapping
S1D13706
Pin Names
NEC VR4181A
AB[16:0] A[16:0]
DB[15:0] D[15:0]
WE1# #UBE
CS# #LCDCS
M/R# A17
CLKI SYSCLK
BS# Connect to HIO V
DD
RD/WR# Connect to HIO V
DD
RD# #MEMRD
WE0# #MEMWR
WAIT# IORDY
RESET# RESET#