Epson Research and Development
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Vancouver Design Center
Interfacing to the NEC VR4181A™ Microprocessor S1D13706
Issue Date: 01/02/23 X31B-G-008-02
4.2 S1D13706 Hardware Configuration
The S1D13706 uses CNF7 through CNF0 to allow selection of the bus mode and other
configuration data on the rising edge of RESET#. For details on configuration, refer to the
S1D13706 Hardware Functional Specification, document number X31B-A-001-xx.
The following table shows the configuration required for this implementation of a
S1D13706 to NEC VR181A interface.
Table 4-1: Summary of Power-On/Reset Configuration Options
S1D1370
6 Pin
Name
value on this pin at the rising edge of RESET# is used to configure: (1/0)
10
CNF[2:0]
100 = Generic #2 Host Bus Interface
CNF3 GPIO pins as inputs at power on GPIO pins as HR-TFT / D-TFT outputs
CNF4
Big Endian bus interface Little Endian bus interface
CNF5
Active high WAIT# Active low WAIT#
CNF[7:6] see Table “” for recommended setting
= configuration for NEC VR4181A
Table 4-2: CLKI to BCLK Divide Selection
CNF7 CNF6 CLKI to BCLK Divide
0 0 1:1
012:1
103:1
114:1
= recommended setting for NEC VR4181A
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