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Epson Research and Development
Vancouver Design Center
S1D13706 Hardware Functional Specification
X31B-A-001-08 Issue Date: 01/11/13
4.4.2 LCD Interface
Table 4-4: LCD Interface Pin Descriptions
Pin Name Type Pin # Cell
IO
Voltage
RESET#
State
Description
FPDAT[17:0] O
74-64,
61-55
LB3P NIOVDD 0 Panel Data bits 17-0.
FPFRAME O 52 LB3P NIOVDD 0
This output pin has multiple functions.
•Frame Pulse
• SPS for Sharp HR-TFT
• DY for Epson D-TFD
See Table 4-10: “LCD Interface Pin Mapping,” on page 31
for
summary.
FPLINE O 53 LB3P NIOVDD 0
This output pin has multiple functions.
• Line Pulse
• LP for Sharp HR-TFT
• LP for Epson D-TFD
See Table 4-10: “LCD Interface Pin Mapping,” on page 31
for
summary.
FPSHIFT O 54 LB3P NIOVDD 0
This output pin has multiple functions.
• Shift Clock
• CLK for Sharp HR-TFT
• XSCL for Epson D-TFD
See Table 4-10: “LCD Interface Pin Mapping,” on page 31
for
summary.
DRDY O 48 LO3 NIOVDD 0
This output pin has multiple functions.
• Display enable (DRDY) for TFT panels
• 2nd shift clock (FPSHIFT2) for passive LCD with Format 1
interface
• GCP for Epson D-TFD
• LCD backplane bias signal (MOD) for all other LCD panels
See Table 4-10: “LCD Interface Pin Mapping,” on page 31
for
summary.
GPIO0 IO 45 LB3M NIOVDD 0
This pin has multiple functions.
• PS for Sharp HR-TFT
• XINH for Epson D-TFD
• General purpose IO pin 0 (GPIO0)
• Hardware Video Invert
See Table 4-10: “LCD Interface Pin Mapping,” on page 31
for
summary.
GPIO1 IO 44 LB3M NIOVDD 0
This pin has multiple functions.
• CLS for Sharp HR-TFT
• YSCL for Epson D-TFD
• General purpose IO pin 1 (GPIO1)
See Table 4-10: “LCD Interface Pin Mapping,” on page 31
for
summary.
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