Epson S1D13706 - Table 4-5: Clock Input Pin Descriptions; Table 4-6: Miscellaneous Pin Descriptions; Table 4-7: Power and Ground Pin Descriptions

Page 28
Epson Research and Development
Vancouver Design Center
S1D13706 Hardware Functional Specification
X31B-A-001-08 Issue Date: 01/11/13
4.4.3 Clock Input
4.4.4 Miscellaneous
4.4.5 Power And Ground
Table 4-5: Clock Input Pin Descriptions
Pin Name Type Pin # Cell
IO
Voltage
RESET#
State
Description
CLKI I 15 LI NIOVDD —
Typically used as input clock source for bus clock and memory
clock
CLKI2 I 77 LI NIOVDD — Typically used as input clock source for pixel clock
Table 4-6: Miscellaneous Pin Descriptions
Pin Name Type Pin # Cell
IO
Voltage
RESET#
State
Description
CNF[7:0] I 78-85 LI NIOVDD —
These inputs are used to configure the S1D13706 - see Table 4-8:
“Summary of Power-On/Reset Options,” on page 29.
Note: These pins are used for configuration of the S1D13706
and must be connected directly to IO V
DD
or V
SS
.
GPO O 47 LO3 NIOVDD 0
General Purpose Output (possibly used for controlling the LCD
power). It may also be used for the MOD control signal of the Sharp
HR-TFT panel.
TESTEN I 86 T1 NIOVDD 0
Test Enable input used for production test only (has type 1 pull-
down resistor with a typical value of 50
Ω
at 3.3V).
Table 4-7: Power And Ground Pin Descriptions
Pin Name Type Pin # Cell
IO
Voltage
RESET#
State
Description
HIOVDD P 16, 26 P — —
IO V
DD
pins associated with the host interface pins as described in
Section 4.4.1, “Host Interface” on page 22.
NIOVDD P
37, 49,
63, 76
P——
IO V
DD
pins associated with the non-host interface pins as
described in Section 4.4.2, “LCD Interface” on page 26, Section
4.4.3, “Clock Input” on page 28, and Section 4.4.4, “Miscellaneous”
on page 28.
COREVDD P 1, 51 P — — 2 Core V
DD.
pins.
VSS P
14, 25,
36, 50,
62, 75,
100
P——7 V
SS
pins.