Epson S1D13706 - CPU Interface Timing; Figure 6-2: Generic #1 Interface Timing

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Epson Research and Development
Vancouver Design Center
S1D13706 Hardware Functional Specification
X31B-A-001-08 Issue Date: 01/11/13
6.2 CPU Interface Timing
The following section includes CPU interface AC Timing for both 2.0V and 3.3V. The
2.0V timings are based on HIO V
DD
= Core V
DD
= 2.0V. The 3.3V timings are based on
HIO V
DD
= Core V
DD
= 3.3V.
6.2.1 Generic #1 Interface Timing
Figure 6-2: Generic #1 Interface Timing
A[16:1]
RD0#,RD1#
D[15:0](write)
M/R#
WAIT#
CLK
T
CLK
t1 t2
t3
t11
t9
t10
WE0#,WE1#
t13
D[15:0](read)
t4
t6
t12
t14
t15
CS#
t5
t8
t7
VALID