Epson Research and Development
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Vancouver Design Center
Interfacing to the Motorola MC68030 Microprocessor S1D13706
Issue Date: 01/02/23 X31B-G-013-02
4.2 S1D13706 Hardware Configuration
The S1D13706 uses CNF7 through CNF0 to allow selection of the bus mode and other
configuration data on the rising edge of RESET#. For details on configuration, refer to the
S1D13706 Hardware Functional Specification, document number X31B-A-001-xx.
The following table shows the configuration required for this implementation of a
S1D13706 to Motorola MC68030 microprocessor.
4.3 Register/Memory Mapping
The MC68030 IDP board uses the first 256M bytes of address space, therefore the
S1D13706 can be mapped anywhere beyond this boundary. The S1D13706 uses two 128K
byte blocks which are selected using M/R# from the address decoder. The internal registers
occupy the first 128K bytes block and the 80K byte display buffer occupies the second
128K byte block. Registers were located at memory location 10A0 0000h and the display
buffer at memory location 10E0 0000h. The address space for the S1D13706 is user
dependent.
Table 4-1: Summary of Power-On/Reset Configuration Options
S1D13706 Pin
Name
value on this pin at the rising edge of RESET# is used to configure: (1/0)
10
CNF[2:0]
010 = MC68K #2 Host Bus Interface
CNF3 GPIO pins as inputs at power on GPIO pins as HR-TFT / D-TFT outputs
CNF4
Big Endian bus interface Little Endian bus interface
CNF5 Active high WAIT# Active low WAIT#
CNF[7:6] see Table “” for recommended settings
= configuration for MC68030 microprocessor
Table 4-2: CLKI to BCLK Divide Selection
CNF7 CNF6 CLKI to BCLK Divide
0 0 1:1
012:1
103:1
114:1
= recommended setting for MC68030 microprocessor
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