Epson S1D13706 - Figure 6-28: 18-Bit TFT Panel Timing

Epson Research and Development
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Hardware Functional Specification S1D13706
Issue Date: 01/11/13 X31B-A-001-08
6.4.9 9/12/18-Bit TFT Panel Timing
Figure 6-28: 18-Bit TFT Panel Timing
VDP = Vertical Display Period
= VDP Lines
VNDP = Vertical Non-Display Period
= VNDP1 + VNDP2
= VT - VDP Lines
VNDP1 = Vertical Non-Display Period 1
= VNDP - VNDP2 Lines
VNDP2 = Vertical Non-Display Period 2
= VDPS - VPS Lines if negative add VT
HDP = Horizontal Display Period
= HDP Ts
HNDP = Horizontal Non-Display Period
= HNDP1 + HNDP2
= HT - HDP Ts
HNDP1 = Horizontal Non-Display Period 1
= HDPS - HPS Ts if negative add HT
HNDP2 = Horizontal Non-Display Period 2
= HPS - (HDP + HDPS) Ts if negative add HT
FPFRAME
FPLINE
LINE1 LINE480
1-1 1-2 1-320
FPLINE
FPSHIFT
DRDY
FPDAT[17:0]
VDP
DRDY
Note: DRDY is used to indicate the first pixel
Example Timing for 18-bit 320x240 panel
VNDP
2
HDP
HNDP
1
HNDP
2
LINE240
VNDP
1
FPDAT[17:0]
invalid
invalid