Epson S1D13706 - Table 6-2: Clock Input Requirements for CLKI When CLKI to BCLK Divide = 1; Table 6-3: Clock Input Requirements for CLKI2

Page 34
Epson Research and Development
Vancouver Design Center
S1D13706 Hardware Functional Specification
X31B-A-001-08 Issue Date: 01/11/13
Note
Maximum internal requirements for clocks derived from CLKI must be considered
when determining the frequency of CLKI. See Section 6.1.2, “Internal Clocks” on page
35 for internal clock requirements.
Note
Maximum internal requirements for clocks derived from CLKI2 must be considered
when determining the frequency of CLKI2. See Section 6.1.2, “Internal Clocks” on page
35 for internal clock requirements.
Table 6-2: Clock Input Requirements for CLKI when CLKI to BCLK divide = 1
Symbol Parameter
2.0V 3.3V
Units
Min Max Min Max
f
OSC
Input Clock Frequency (CLKI) 20 66 MHz
T
OSC
Input Clock period (CLKI) 1/f
OSC
1/f
OSC
ns
t
PWH
Input Clock Pulse Width High (CLKI) 3 3 ns
t
PWL
Input Clock Pulse Width Low (CLKI) 3 3 ns
t
f
Input Clock Fall Time (10% - 90%) 5 5 ns
t
r
Input Clock Rise Time (10% - 90%) 5 5 ns
Table 6-3: Clock Input Requirements for CLKI2
Symbol Parameter
2.0V 3.3V
Units
Min Max Min Max
f
OSC
Input Clock Frequency (CLKI2) 20 66 MHz
T
OSC
Input Clock period (CLKI2) 1/f
OSC
1/f
OSC
ns
t
PWH
Input Clock Pulse Width High (CLKI2) 3 3 ns
t
PWL
Input Clock Pulse Width Low (CLKI2) 3 3 ns
t
f
Input Clock Fall Time (10% - 90%) 5 5 ns
t
r
Input Clock Rise Time (10% - 90%) 5 5 ns