Epson S1D13706 - Table 8-19: PWMOUT Duty Cycle Select Options

Epson Research and Development
Page 129
Vancouver Design Center
Hardware Functional Specification S1D13706
Issue Date: 01/11/13 X31B-A-001-08
bits 7-0 CV Pulse Burst Length Bits [7:0]
The value of this register determines the number of pulses generated in a single CV Pulse
burst:
Number of pulses in a burst = (ContentsOfThisRegister) + 1
bits 7-0 PWMOUT Duty Cycle Bits [7:0]
This register determines the duty cycle of the PWMOUT output.
CV Pulse Burst Length Register
REG[B2h] Read/Write
CV Pulse Burst Length Bits 7-0
76543210
PWMOUT Duty Cycle Register
REG[B3h] Read/Write
PWMOUT Duty Cycle Bits 7-0
76543210
Table 8-19: PWMOUT Duty Cycle Select Options
PWMOUT Duty Cycle [7:0] PWMOUT Duty Cycle
00h Always Low
01h High for 1 out of 256 clock periods
02h High for 2 out of 256 clock periods
... ...
FFh High for 255 out of 256 clock periods