Epson S1D13706 - Table 6-7: Hitachi SH-4 Interface Timing

Epson Research and Development
Page 41
Vancouver Design Center
Hardware Functional Specification S1D13706
Issue Date: 01/11/13 X31B-A-001-08
1. t15 is the delay from when data is placed on the bus until the data is latched into the write buffer.
Note
Minimum one software WAIT state is required.
Table 6-7: Hitachi SH-4 Interface Timing
Symbol Parameter
2.0V 3.3V
Unit
MinMaxMinMax
f
CKIO
Clock frequency
20 66 MHz
T
CKIO
Clock period
1/f
CKIO
1/f
CKIO
ns
t1
Clock pulse width low
22.5 6.8 ns
t2
Clock pulse width high
22.5 6.8 ns
t3
A[16:1], M/R#, RD/WR# setup to CKIO
01ns
t4
A[16:1], M/R#, RD/WR# hold from CSn#
00ns
t5
BS# setup
31ns
t6
BS# hold
72ns
t7
CSn# setup
01ns
t8
CSn# high setup to CKIO
02ns
t9a
RD# or WEn# asserted for MCLK = BCLK (max. MCLK = 50MHz)
8.5 8.5 T
CKIO
t9b
RD# or WEn# asserted for MCLK = BCLK
÷
2
11.5 11.5 T
CKIO
t9c
RD# or WEn# asserted for MCLK = BCLK
÷
3
13.5 13.5 T
CKIO
t9d
RD# or WEn# asserted for MCLK = BCLK
÷
4
18.5 18.5 T
CKIO
t10
Falling edge RD# to D[15:0] driven (read cycle)
524312ns
t11
Falling edge CSn# to RDY# driven high
319312ns
t12
CKIO to RDY# low
542418ns
t13
CSn# high to RDY# high
535414ns
t14
Falling edge CKIO to RDY# high impedance
538414ns
t15
D[15:0] setup to 2
nd
CKIO after BS# (write cycle) (see note 1)
10ns
t16
D[15:0] hold (write cycle)
00ns
t17
RDY# falling edge to D[15:0] valid (read cycle)
02ns
t18
Rising edge RD# to D[15:0] high impedance (read cycle)
531312ns