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Epson Research and Development
Vancouver Design Center
S1D13706 Integrating the CFLGA 104-pin Chip Scale Package
X31B-G-018-02 Issue Date: 01/02/26
2 Package Description
Designing a Chip Scale Package part (i.e. S1D13706) into a printed circuit board requires
the use of microvia technology. Before starting development of a PCB, consult with the
board manufacturer for information about the particular microvia technology they use.
Microvias are commonly defined as vias that have holes less than 0.15mm (0.006") in
diameter. Microvia technology typically uses the layer located just below the outermost
layer. Microvias are blind vias that go down only one layer and connect the outer layer with
the microvia specific layer. The traces on microvia specific layers are connected to the other
layers of the board by standard vias.
The S1D13706 CSP has the following characteristics.
• reinforced land type footprint.
• 4 reinforced pads, land size 1.05mm (.042") in diameter.
• 104 pads.
• land size 0.3mm (0.012") in diameter.
• distributed on a 11 x 11 grid with a 0.65mm (0.025") pitch.
• solder mask 0.43mm (0.017") in diameter.
Note
The reinforcement pads located in the corner of the footprint, provide extra mechanical
strength once the chip has been mounted.
For pinout diagrams and mechanical drawings, see the S1D13706 Hardware Functional
Specification, document number X31B-A-001-xx.
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