Epson S1D13706 - 2 Motorola MC68030 Bus Interface; Overview; Dynamic Bus Sizing; Asynchronous; Synchronous Bus Operation

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Epson Research and Development
Vancouver Design Center
S1D13706 Interfacing to the Motorola MC68030 Microprocessor
X31B-G-013-02 Issue Date: 01/02/23
2 Motorola MC68030 Bus Interface
2.1 Overview
The MC68030 is a second generation enhanced microprocessor from the Motorola M68000
family of devices. The MC68030 is a 32-bit microprocessor with a 32-bit address bus and
a 32-bit data bus. The microprocessor supports both asynchronous and synchronous bus
cycles and burst data transfers. The bus also supports dynamic bus sizing which automati-
cally determines device port size on a cycle-by-cycle basis.
2.2 Dynamic Bus Sizing
The MC68030 supports dynamic bus sizing using the following signals.
• SIZ1 and SIZ0 indicate the number of bytes remaining to be transfered for the current
bus cycle.
• DSACK1 and DSACK0 (the data transfer size acknowledge signals) indicate the size of
the external port and acknowledge the end of the cycle.
• A0 and A1 determine which portion of the data bus the data is transferred on and
whether the address is misaligned.
2.3 Asynchronous / Synchronous Bus Operation
The MC68030 bus can operate asynchronously or synchronously. Asynchronous operation
requires DSACK0
, DSACK1, AS, and DS to control transfers. The DSACK signals
specify the port width and insert wait states in the current bus cycle. AS
(the address strobe)
Table 2-1: SIZ Signal Encoding
SIZ1 SIZ0 Bytes Remaining
01 1 Byte
1 0 2 Bytes (Word)
11 3 Bytes
0 0 4 Bytes (Double Word)
Table 2-2: DSACK Decoding
DSACK1 DSACK0 Result
1 1 Insert Wait States in the Current Bus Cycle
1 0 Complete Cycle - Data Bus Port Size is 8 bits
0 1 Complete Cycle - Data Bus Port Size is 16 bits
0 0 Complete Cycle - Data Bus Port Size is 32 bits