Page 8
Epson Research and Development
Vancouver Design Center
S1D13706 Integrating the CFLGA 104-pin Chip Scale Package
X31B-G-018-02 Issue Date: 01/02/26
3.2 Inner Pads
The inner pads on top layer require microvias connecting them with the microvia specific
layer located just below the top layer. The pads on the microvia specific layer have a land
size of 0.254mm (0.010") in diameter and are fanned out with 0.005" traces with 0.005"
spaces at the passage between pads.
All the Vss pins are inner pins and require connection with the microvia specific layer. On
this layer, all the Vss pads are connected together and are fanned out with multiple traces.
All the traces on the microvia specific layer must be terminated to a standard through-hole
via for connection to the rest of the board (i.e. bottom layer, power and ground planes).
The following diagram shows an example for inner pad routing.
Figure 3-2: Example Inner Pad Routing
To Next Page
Loading...