Epson S1D13706 - Figure 6-12: Passive;Tft Power-Off Sequence Timing; Table 6-15: Passive;Tft Power-Off Sequence Timing

Epson Research and Development
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Vancouver Design Center
Hardware Functional Specification S1D13706
Issue Date: 01/11/13 X31B-A-001-08
6.3.2 Passive/TFT Power-Off Sequence
Figure 6-12: Passive/TFT Power-Off Sequence Timing
1. t1 is controlled by software and must be determined from the bias power supply delay requirements of the panel
connected.
Table 6-15: Passive/TFT Power-Off Sequence Timing
Symbol Parameter Min Max Units
t1
LCD bias deactivated to LCD signals inactive
Note 1 Note 1
t2
Power Save Mode enabled to LCD signals low
020ns
LCD Signals***
GPO*
t1
*It is recommended to use the general purpose output pin GPO to control the LCD bias power.
**The LCD power-off sequence is activated by programming the Power Save Mode Enable bit (REG[A0h] bit 0) to 1.
***LCD Signals include: FPDAT[17:0], FPSHIFT, FPLINE, FPFRAME, and DRDY.
t2
Power Save
(REG[A0h] bit 0)
Mode Enable**