Epson S1D13706 - LCD Memory Access Cycles

Epson Research and Development
Page 9
Vancouver Design Center
Interfacing to the NEC VR4102 / VR4111 Microprocessors S1D13706
Issue Date: 01/02/23 X31B-G-007-02
2.1.2 LCD Memory Access Cycles
Once an address in the LCD block of memory is placed on the external address bus
(ADD[25:0]) the LCD chip select (LCDCS#) is driven low. The read enable (RD#) or write
enable (WR#) signals are driven low for the appropriate cycle. LCDRDY is driven low by
the S1D13706 to insert wait states into the cycle. The system high byte enable is driven low
for 16-bit transfers and high for 8-bit transfers.
Figure 2-1: “NEC VR4102/VR4111 Read/Write Cycles,” shows the read and write cycles
to the LCD Controller Interface.
Figure 2-1: NEC VR4102/VR4111 Read/Write Cycles
TCLK
ADD[25:0]
LCDCS#
WR#,RD#
LCDRDY
VALID
VALID
VALID
Hi-Z
Hi-Z
D[15:0]
D[15:0]
(write)
(read)
SHB#