Epson S1D13706 - Table 6-8: Hitachi SH-3 Interface Timing

Epson Research and Development
Page 43
Vancouver Design Center
Hardware Functional Specification S1D13706
Issue Date: 01/11/13 X31B-A-001-08
1. t14 is the delay from when data is placed on the bus until the data is latched into the write buffer.
Note
Minimum one software WAIT state is required.
Table 6-8: Hitachi SH-3 Interface Timing
Symbol Parameter
2.0V 3.3V
Unit
MinMaxMinMax
f
CKIO
Bus Clock frequency
20 66 MHz
T
CKIO
Bus Clock period
1/f
CKIO
1/f
CKIO
ns
t1
Bus Clock pulse width low
22.5 6.8 ns
t2
Bus Clock pulse width high
22.5 6.8 ns
t3
A[16:1], M/R#, RD/WR# setup to CKIO
01ns
t4
CSn# high setup to CKIO
01ns
t5
BS# setup
31ns
t6
BS# hold
72ns
t7
CSn# setup
01ns
t8
A[16:1], M/R#, RD/WR# hold from CS#
00ns
t9a
RD# or WEn# asserted for MCLK = BCLK (max. MCLK = 50MHz)
8.5 8.5 T
CKIO
t9b
RD# or WEn# asserted for MCLK = BCLK
÷
2
11.5 11.5 T
CKIO
t9c
RD# or WEn# asserted for MCLK = BCLK
÷
3
13.5 13.5 T
CKIO
t9d
RD# or WEn# asserted for MCLK = BCLK
÷
4
18.5 18.5 T
CKIO
t10
Falling edge RD# to D[15:0] driven (read cycle)
524312ns
t11
Rising edge CSn# to WAIT# high impedance
424210ns
t12
Falling edge CSn# to WAIT# driven low
324212ns
t13
CKIO to WAIT# delay
645418ns
t14
D[15:0] setup to 2
nd
CKIO after BS# (write cycle) (see note 1)
10ns
t15
D[15:0] hold (write cycle)
00ns
t16
WAIT# rising edge to D[15:0] valid (read cycle)
02ns
t17
Rising edge RD# to D[15:0] high impedance (read cycle)
531312ns