Epson S1D13706 - Table 6-6: Generic #2 Interface Timing

Epson Research and Development
Page 39
Vancouver Design Center
Hardware Functional Specification S1D13706
Issue Date: 01/11/13 X31B-A-001-08
1. t11 is the delay from when data is placed on the bus until the data is latched into the write buffer.
Table 6-6: Generic #2 Interface Timing
Symbol Parameter
2.0V 3.3V
Unit
MinMaxMinMax
f
BUSCLK
Bus Clock frequency 20 50 MHz
T
BUSCLK
Bus Clock period 1/f
BUSCLK
1/f
BUSCLK
ns
t1 Clock pulse width high 22.5 9 ns
t2 Clock pulse width low 22.5 9 ns
t3
SA[16:0], M/R#, SBHE# setup to first BUSCLK rising edge
where CS# = 0 and either MEMR# = 0 or MEMW# = 0
11ns
t4
SA[16:0], M/R#, SBHE# hold from either MEMR# or MEMW#
rising edge
00ns
t5 CS# setup to BUSCLK rising edge 0 1 ns
t6 CS# hold from either MEMR# or MEMW# rising edge 0 0 ns
t7a MEMR#/MEMW# asserted for MCLK = BCLK 8.5 8 T
BUSCLK
t7b MEMR#/MEMW# asserted for MCLK = BCLK
÷
211.511T
BUSCLK
t7c MEMR#/MEMW# asserted for MCLK = BCLK
÷
313.513T
BUSCLK
t7d MEMR#/MEMW# asserted for MCLK = BCLK
÷
417.517T
BUSCLK
t8 MEMR# or MEMW# setup to BUSCLK rising edge 2 1 ns
t9
Falling edge of either MEMR# or MEMW# to IOCHRDY driven
low
5315ns
t10
Rising edge of either MEMR# or MEMW# to IOCHRDY high
impedance
5313ns
t11
SD[15:0] setup to third BUSCLK rising edge where CS# = 0 and
MEMW# = 0 (write cycle) (see note 1)
10ns
t12 SD[15:0] hold from IOCHRDY rising edge (write cycle) 1 0 ns
t13 MEMR# falling edge to SD[15:0] driven (read cycle) 4 26 3 13 ns
t14 IOCHRDY rising edge to SD[15:0] valid (read cycle) 0 2 ns
t15
Rising edge of MEMR# to SD[15:0] high impedance (read
cycle)
533312ns