Epson Research and Development
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Vancouver Design Center
Integrating the CFLGA 104-pin Chip Scale Package S1D13706
Issue Date: 01/02/26 X31B-G-018-02
1 Introduction
This manual provides an example for integrating the CFLGA 104-pin chip scale package
(CSP) available for the S1D13706. It includes an overview of the package and provides an
example of how to route the pads.
This application note is updated as appropriate. Please check the Epson Electronics
America website at www.eea.epson.com or the Epson Research and Development website
at www.erd.epson.com for the latest revision of this document before beginning any devel-
opment.
We appreciate your comments on our documentation. Please contact us via email at
documentation@erd.epson.com.
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