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Epson Research and Development
Vancouver Design Center
S1D13706 Interfacing to the PC Card Bus
X31B-G-005-02 Issue Date: 01/02/23
4 PC Card to S1D13706 Interface
4.1 Hardware Connections
The S1D13706 is interfaced to the PC Card bus with a minimal amount of glue logic. In
this implementation, the address inputs (AB[16:0]) and data bus (DB[15:0] connect directly
to the CPU address (A[16:0]) and data bus (D[15:0]).
The PC Card interface does not provide a bus clock, so one must be supplied for the
S1D13706. Since the bus clock frequency is not critical, nor does it have to be synchronous
to the bus signals, it may be the same as CLKI2.
BS# (bus start) and RD/WR# are not used by the Generic #2 Host Bus Interface and should
be tied high (connected to HIO V
DD
).
The following diagram shows a typical implementation of the PC Card to S1D13706
interface.
Figure 4-1: Typical Implementation of PC Card to S1D13706 Interface
RD/WR#
RD#
DB[15:0]
WAIT#
CLKI
S1D13706
RESET#
AB[16:0]
-OE
D[15:0]
-WAIT
A[16:0]
PC Card Bus
15K pull-up
CLKI2
Oscillator
WE1#
WE0#
CS#
-WE
-CE1
-CE2
RESET
HIO V
DD
BS#
Note:
When connecting the S1D13706 RESET# pin, the system designer should be aware of all
conditions that may reset the S1D13706 (e.g. CPU reset can be asserted during wake-up
from power-down modes, or during debug states).
A17
M/R#
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