Epson S1D13706 - LCD Pin Mapping for y Connector (LF37 SQT)

Page 16
Epson Research and Development
Vancouver Design Center
S1D13706 Connecting to the Epson D-TFD Panels
X31B-G-012-03 Issue Date: 01/02/23
3.2 LCD Pin Mapping for Y Connector (LF37SQT)
Table 3-2: LCD Pin Mapping for Y Connector: Pins for Y - Driver (LF37SQT)
LCD Pin
No.
LCD Pin
Name
S1D13706
Pin Name
Description Remarks
Y-1 GND VSS (GND)
Ground and power supply for liquid crystal
drive
Y-2 SHF - Shift direction selection for shift registers
Forward scanning: V5Y
Reverse scanning: VCCY
Connect to VCCY.
Y-3 XINH GPIO0 Thinning control signal
See Section 2.5, “Level Shift and Clamp
Circuit for Vertical Logic Control Signals”
on page 13.
Y-4 YSCL GPIO1 Shift clock signal
See Section 2.5, “Level Shift and Clamp
Circuit for Vertical Logic Control Signals”
on page 13.
Y-5 FRY GPIO2 AC signal for output
See Section 2.5, “Level Shift and Clamp
Circuit for Vertical Logic Control Signals”
on page 13.
Y-6 VCCY - Power supply for logic high
See Section 2.4, “Swing Power Supply for
the Vertical Drive (V0Y) and Logic (VCCY
/ V5Y) Voltages” on page 12.
Y-7 V5Y -
Power supply for logic low and liquid crystal
drive
See Section 2.4, “Swing Power Supply for
the Vertical Drive (V0Y) and Logic (VCCY
/ V5Y) Voltages” on page 12.
Y-8 NC - No Connect
Y-9 V0Y - Power supply for liquid crystal drive
See Section 2.4, “Swing Power Supply for
the Vertical Drive (V0Y) and Logic (VCCY
/ V5Y) Voltages” on page 12.
Y-10 VDD - Power supply for liquid crystal drive
See Section 2.1, “VDDH and VDD -
Horizontal and Vertical Analog Voltages”
on page 8.
Y-11 DYIO2 No Connect Start pulse signal
Forward scanning: Active low pulse
Reverse scanning: Open
Y-12 DYIO1 FPFRAME Start pulse signal
Forward scanning: Open
Reverse scanning: Active low pulse
See Section 2.5, “Level Shift and Clamp
Circuit for Vertical Logic Control Signals”
on page 13.