Epson S1D13706 - Table 6-9: Motorola MC68 K #1 Interface Timing

Epson Research and Development
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Hardware Functional Specification S1D13706
Issue Date: 01/11/13 X31B-A-001-08
1. t17 is the delay from when data is placed on the bus until the data is latched into the write buffer.
Table 6-9: Motorola MC68K #1 Interface Timing
Symbol Parameter
2.0V 3.3V
Unit
MinMaxMinMax
f
CLK
Bus Clock Frequency 20 50 MHz
T
CLK
Bus Clock period 1/f
CLK
1/f
CLK
ns
t1 Clock pulse width high 22.5 9 ns
t2 Clock pulse width low 22.5 9 ns
t3
A[16:1], M/R# setup to first CLK rising edge where CS# = 0,
AS# = 0, UDS# = 0, and LDS# = 0
11ns
t4 A[16:1], M/R# hold from AS# rising edge 0 0 ns
t5 CS# setup to CLK rising edge while CS#, AS#, UDS#/LDS# = 0 0 1 ns
t6 CS# hold from AS# rising edge 0 0 ns
t7a AS# asserted for MCLK = BCLK 8 8 T
CLK
t7b AS# asserted for MCLK = BCLK
÷
21111T
CLK
t7c AS# asserted for MCLK = BCLK
÷
31313T
CLK
t7d AS# asserted for MCLK = BCLK
÷
41818T
CLK
t8 AS# setup to CLK rising edge while CS#, AS#, UDS#/LDS# = 0 1 1 ns
t9 AS# setup to CLK rising edge 1 2 ns
t10
UDS#/LDS# setup to CLK rising edge while CS#, AS#,
UDS#/LDS# = 0
31ns
t11 UDS#/LDS# high setup to CLK rising edge 3 2 ns
t12 First CLK rising edge where AS# = 1 to DTACK# high impedance 5 40 3 14 ns
t13
R/W# setup to CLK rising edge before all CS#, AS#, UDS# and/or
LDS# = 0
01ns
t14 R/W# hold from AS# rising edge 0 0 ns
t15 AS# = 0 and CS# = 0 to DTACK# driven high 4 23 3 13 ns
t16 AS# rising edge to DTACK# rising edge 6 39 4 16 ns
t17
D[15:0] valid to third CLK rising edge where CS# = 0, AS# = 0 and
either UDS# = 0 or LDS# = 0 (write cycle) (see note 1)
10ns
t18 D[15:0] hold from DTACK# falling edge (write cycle) 0 0 ns
t19 UDS# = 0 and/or LDS# = 0 to D[15:0] driven (read cycle) 4 27 3 13 ns
t20 DTACK# falling edge to D[15:0] valid (read cycle) 0 2 ns
t21 UDS#, LDS# rising edge to D[15:0] high impedance (read cycle) 5 33 3 13 ns