Epson S1D13706 - Table 8-17: PWM Clock Divide Select Options; Table 8-18: CV Pulse Divide Select Options

Page 128
Epson Research and Development
Vancouver Design Center
S1D13706 Hardware Functional Specification
X31B-A-001-08 Issue Date: 01/11/13
bits 7-4 PWM Clock Divide Select Bits [3:0]
The value of these bits represents the power of 2 by which the selected PWM clock source
is divided.
Note
This divided clock is further divided by 256 before it is output at PWMOUT.
bits 3-1 CV Pulse Divide Select Bits [2:0]
The value of these bits represents the power of 2 by which the selected CV Pulse source is
divided.
Note
This divided clock is further divided by 2 before it is output at the CVOUT.
bit 0 PWMCLK Source Select
When this bit = 0, the clock source for PWMCLK is CLKI.
When this bit = 1, the clock source for PWMCLK is CLKI2.
Note
For further information on the PWMCLK source select, see Section 7.2, “Clock Selec-
tion” on page 93.
PWM Clock / CV Pulse Configuration Register
REG[B1h] Read/Write
PWM Clock Divide Select Bits 3-0 CV Pulse Divide Select Bits 2-0
PWMCLK
Source Select
76543210
Table 8-17: PWM Clock Divide Select Options
PWM Clock Divide Select Bits [3:0] PWM Clock Divide Amount
0h 1
1h 2
2h 4
3h 8
... ...
Ch 4096
Dh-Fh Reserved
Table 8-18: CV Pulse Divide Select Options
CV Pulse Divide Select Bits [2:0] CV Pulse Divide Amount
0h 1
1h 2
2h 4
3h 8
... ...
7h 128