Epson S1D13706 - 4 Toshiba TMPR3905;12 to S1 D13706 Interface; Hardware Description

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Epson Research and Development
Vancouver Design Center
S1D13706 Interfacing to the Toshiba MIPS TMPR3905/3912 Microprocessors
X31B-G-002-02 Issue Date: 01/02/23
4 Toshiba TMPR3905/12 to S1D13706 Interface
4.1 Hardware Description
In this implementation, the S1D13706 occupies the TMPR3905/12 PC Card slot #1 IO
address space. IO address space closely matches the timing parameters for the S1D13706
Generic #2 Host Bus Interface.
The address bus of the TMPR3905/12 PC Card interface is multiplexed and must be demul-
tiplexed using an advanced CMOS latch (e.g., 74AHC373).
BS# (bus start) and RD/WR# are not used in this implementation and should be tied high
(connected to HIO V
DD
).
A pull-up resistor is attached to WAIT# to speed up its rise time when terminating a cycle.
The following diagram demonstrates a typical implementation of the TMPR3905/12 to
S1D13706 interface.
Figure 4-1: S1D13706 to TMPR3905/12 Direct Connection
WE0#
RD#
DB[7:0]
WAIT#
S1D13706
RESET#
AB[16:13]
D[31:24]
CARD1WAIT*
A[12:0]
TMPR3905/12
pull-up
Oscillator
WE1#
CARD1CSL*
CARD1CSH*
Latch
ALE
System RESET
CARDIOWR*
CARDIORD*
BS#
RD/WR#
HIO V
DD
ENDIAN
DB[15:8]
D[23:16]
AB[12:0]
HIOVDD
DCLKOUT
...or...
CS#
CLKI2
See text
Clock divider
HIO V
DD
, CORE V
DD
+3.3V
Note:
When connecting the S1D13706 RESET# pin, the system designer should be aware of all
conditions that may reset the S1D13706 (e.g. CPU reset can be asserted during wake-up
from power-down modes, or during debug states).
CLKI
A17
M/R#