Epson Research and Development
Page 13
Vancouver Design Center
Interfacing to the Toshiba MIPS TMPR3905/3912 Microprocessors S1D13706
Issue Date: 01/02/23 X31B-G-002-02
The Generic #2 Host Bus Interface control signals of the S1D13706 are asynchronous with
respect to the S1D13706 bus clock. This gives the system designer full flexibility to choose
the appropriate source (or sources) for CLKI and CLKI2. The choice of whether both
clocks should be the same, and whether to use DCLKOUT (divided) as clock source,
should be based on the desired:
• pixel and frame rates.
• power budget.
•part count.
• maximum S1D13706 clock frequencies.
The S1D13706 also has internal clock dividers providing additional flexibility.
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