Epson S1D13706 - Table 6-13: Motorola Dragonball Interface Without DTACK Timing

Epson Research and Development
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Hardware Functional Specification S1D13706
Issue Date: 01/11/13 X31B-A-001-08
1. The MC68EZ328 cannot support the MCLK = BCLK
÷
3 and MCLK = BCLK
÷
4 settings without DTACK.
2. t12 is the delay from when data is placed on the bus until the data is latched into the write buffer.
Table 6-13: Motorola DragonBall Interface without DTACK Timing
Symbol Parameter
MC68EZ328 MC68VZ328
Unit2.0V 3.3V 2.0V 3.3V
Min Max Min Max Min Max Min Max
f
CLKO
Bus Clock frequency 16 16 20 33 MHz
T
CLKO
Bus Clock period
1/f
CLKO
1/f
CLKO
1/f
CLKO
1/f
CLKO
ns
t1 Clock pulse width high 28.1 28.1 22.5 13.6 ns
t2 Clock pulse width low 28.1 28.1 22.5 13.6 ns
t3
A[16:1] setup 1st CLKO when CSX
= 0 and
either UWE
/LWE or OE = 0
00 00ns
t4 A[16:1] hold from CSX rising edge 0 0 0 0 ns
t5a
CSX asserted for MCLK = BCLK
(CPU wait state register should be programmed
to 4 wait states)
8888T
CLKO
t5b
CSX
asserted for MCLK = BCLK
÷
2
(CPU wait state register should be programmed
to 6 wait states)
11 11 11 11 T
CLKO
t5c
CSX
asserted for MCLK = BCLK
÷
3
(CPU wait state register should be programmed
to 10 wait states)
—
Note 1
—
Note 1
13 13 T
CLKO
t5d
CSX
asserted for MCLK = BCLK
÷
4
(CPU wait state register should be programmed
to 12 wait states)
—
Note 1
—
Note 1
17 17 T
CLKO
t6 CSX setup to CLKO rising edge 0 0 0 0 ns
t7 CSX
rising edge setup to CLKO rising edge 0 0 0 0 ns
t8 UWE/LWE setup to CLKO rising edge 1 0 1 0 ns
t9 UWE/LWE rising edge to CSX rising edge 0 0 0 0 ns
t10 OE
setup to CLKO rising edge 1 1 1 1 ns
t11 OE hold from CSX rising edge 0 0 0 0 ns
t12
D[15:0] setup to 3rd CLKO after CSX, UWE/LWE
asserted (write cycle) (see note 2)
10 10ns
t13
CSX
rising edge to D[15:0] output Hi-Z (write
cycle)
00 00ns
t14 Falling edge of OE
to D[15:0] driven (read cycle) 4 30 3 15 4 30 3 15 ns
t15a
1st CLKO rising edge after OE and CSX
asserted low to D[15:0] valid for MCLK = BCLK
(read cycle)
5.5T
CLKO
+ 4
5.5T
CLKO
+ 20
5.5T
CLKO
+ 4
5.5T
CLKO
+ 20
ns
t15b
1st CLKO rising edge after OE
and CSX
asserted low to D[15:0] valid for MCLK = BCLK
÷
2 (read cycle)
8T
CLKO
+
19
8.5T
CLKO
+ 20
8T
CLKO
+
19
8.5T
CLKO
+ 20
ns
t15c
1st CLKO rising edge after OE
and CSX
asserted low to D[15:0] valid for MCLK = BCLK
÷
3 (read cycle)
9.5T
CLKO
+ 17
10.5T
CLKO
+ 20
9.5T
CLKO
+ 17
10.5T
CLKO
+ 20
ns
t15d
1st CLKO rising edge after OE
and CSX
asserted low to D[15:0] valid for MCLK = BCLK
÷
4 (read cycle)
13T
CLKO
+ 9
14.5T
CLKO
+ 20
13T
CLKO
+ 9
14.5T
CLKO
+ 20
ns
t16
CLKO rising edge to D[15:0] output Hi-Z
(read cycle)
4 21 2 12 4 21 2 12 ns