Epson Research and Development
Page 7
Vancouver Design Center
Integrating the CFLGA 104-pin Chip Scale Package S1D13706
Issue Date: 01/02/26 X31B-G-018-02
3 Routing
3.1 Perimeter Pads
Perimeter pads of the S1D13706 CSP are usually fanned out on the top layer using 0.004"
traces with 0.0045" spaces at the passage between pads. The traces are terminated using
standard via technology (i.e. 0.025" via with 0.012" hole).
The following diagram shows an example for perimeter pad routing.
Figure 3-1: Example Perimeter Pad Routing
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