Epson S1D13706 - Registers; Memory Controller Power Save Status; Power Save Mode Enable

Epson Research and Development
Page 27
Vancouver Design Center
Programming Notes and Examples S1D13706
Issue Date: 01/02/23 X31B-G-003-03
5.2 Registers
5.2.1 Power Save Mode Enable
The Power Save Mode Enable bit initiates Power Save Mode when set to 1. Setting the bit
back to 0 returns the S1D13706 back to normal mode.
Note
Enabling/disabling Power Save Mode requires proper LCD Power Sequencing. See Sec-
tion 6, “LCD Power Sequencing” on page 29.
5.2.2 Memory Controller Power Save Status
The Memory Controller Power Save Status bit is a read-only status bit which indicates the
power save state of the S1D13706 SRAM interface. When this bit returns a 1, the SRAM
interface is powered down. When this bit returns a 0, the SRAM interface is active. This bit
returns a 0 after a chip reset.
Note
The memory clock source may be disabled when this bit returns a 1.
REG[A0h] Power Save Configuration Register Read/Write
VNDP Status
(RO)
n/a n/a n/a
Memory
Controller
Power Save
Status (RO)
n/a n/a
Power Save
Mode Enable
REG[A0h] Power Save Configuration Register Read/Write
VNDP Status
(RO)
n/a n/a n/a
Memory
Controller
Power Save
Status (RO)
n/a n/a
Power Save
Mode Enable