Epson Research and Development
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Vancouver Design Center
Interfacing to the Toshiba MIPS TMPR3905/3912 Microprocessors S1D13706
Issue Date: 01/02/23 X31B-G-002-02
1 Introduction
This application note describes the hardware and software environment necessary to
provide an interface between the S1D13706 Embedded Memory LCD Controller and the
Toshiba MIPS TMPR3905/3912 processors.
The designs described in this document are presented only as examples of how such
interfaces might be implemented. This application note is updated as appropriate. Please
check the Epson Electronics America website at http://www.eea.epson.com for the latest
revision of this document before beginning any development.
We appreciate your comments on our documentation. Please contact us via email at
techpubs@erd.epson.com.
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