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Epson Research and Development
Vancouver Design Center
S1D13706 Interfacing to the NEC VR4181A™ Microprocessor
X31B-G-008-02 Issue Date: 01/02/23
2 Interfacing to the NEC VR4181A
2.1 The NEC VR4181A System Bus
The VR-Series family of microprocessors features a high-speed synchronous system bus
typical of modern microprocessors. Designed with external LCD controller support and
Windows® CE based embedded consumer applications in mind, the VR4181A offers a
highly integrated solution for portable systems. This section is an overview of the operation
of the CPU bus to establish interface requirements.
2.1.1 Overview
The NEC VR4181A is designed around the RISC architecture developed by MIPS. This
microprocessor is designed around the 100MHz VR4110 CPU core which supports the
MIPS III and MIPS16 instruction sets. The CPU communicates with external devices via
an ISA interface.
While the VR4181A has an embedded LCD controller, this internal controller can be
disabled to provide direct support for an external LCD controller through its external ISA
bus. A 64 to 512K byte block of memory is assigned to the external LCD controller with a
dedicated chip select signal (LCDCS#). Word or byte accesses are controlled by the system
high byte signal (#UBE).
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