Epson S1D13706 - 4 MC68030 to S1 D13706 Interface; Hardware Description

Page 12
Epson Research and Development
Vancouver Design Center
S1D13706 Interfacing to the Motorola MC68030 Microprocessor
X31B-G-013-02 Issue Date: 01/02/23
4 MC68030 to S1D13706 Interface
4.1 Hardware Description
The interface between the S1D13706 and the MC68030 requires external glue logic.
Address decoding logic is required to provide the chip select (CS#) and memory/register
(M/R#) signals to the S1D13706 since the MC68030 does not have a chip select module.
SIZ1 is modified to signal the S1D13706 that 24-bit and 32-bit accesses are to converted
into word-byte and word-word accesses, respectively. Misaligned operands for 24-bit and
32-bit cycles are not supported with this external circuitry for SIZ1.RD# must be connected
to the following logic circuitry instead of directly to SIZ1.
RD# = ’(SIZ0 & SIZ1’).
The polarity of the WAIT# signal must be selected as active high by connecting CNF5 to
NIO V
DD
(see Table 4-1:, “Summary of Power-On/Reset Configuration Options,” on
page 13).
The diagram below shows a typical implementation of the MC68030 to S1D13706
interface.
Figure 4-1: Typical Implementation of MC68030 to S1D13706 Interface
Note
The interface was designed using a Motorola MC68030 Integrated Development
Platform (IDP).
MC68030 S1D13706
A[16:0]
D[31:16]
DSACK1
DS
SIZ0
R/W
CLK
AB[16:0]
DB[15:0]
CS#
WAIT#
WE1#
WE0#
RD/WR#
RD#
CLKI
RESET#
BS#
System RESET
Note:
When connecting the S1D13706 RESET# pin, the system designer should be aware of all
conditions that may reset the S1D13706 (e.g. CPU reset can be asserted during wake-up
from power-down modes, or during debug states).
M/R#
AS
SIZ1
Decode Logic
FC[2:0]