Epson S1D13706 - Figure 3-1: Typical System Diagram (Generic #1 Bus); Figure 3-2: Typical System Diagram (Generic #2 Bus); Typical System Implementation Diagrams

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Epson Research and Development
Vancouver Design Center
S1D13706 Hardware Functional Specification
X31B-A-001-08 Issue Date: 01/11/13
3 Typical System Implementation Diagrams
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Figure 3-1: Typical System Diagram (Generic #1 Bus)
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Figure 3-2: Typical System Diagram (Generic #2 Bus)
S1D13706
FPLINE
FPFRAME
FPSHIFT
DRDY
FPDAT[15:0]
CLKI2
Oscillator
FPLINE
FPFRAME
FPSHIFT
MOD
D[15:0]
16-bit
Generic #1
BUS
RESET#
D[15:0]
RD0#
WAIT#
A[16:1]
BUSCLK
RD/WR#
AB[16:1]
DB[15:0]
WE1#
RD#
M/R#
CS#
CLKI
WAIT#
RESET#
A[27:17]
CSn#
WE1#
GPO
Decoder
WE0#
WE0#
Single
LCD
Display
Bias Power
BS#
HIOVDD
RD1#
VSS
AB0
S1D13706
FPLINE
FPFRAME
FPSHIFT
DRDY
FPDAT[8:0]
CLKI2
Oscillator
FPLINE
FPFRAME
FPSHIFT
DRDY
D[8:0]
9-bit
Generic #2
BUS
RESET#
D[15:0]
RD#
WAIT#
A[16:0]
BUSCLK
RD/WR#
AB[16:0]
DB[15:0]
WE1#
RD#
M/R#
CS#
CLKI
WAIT#
RESET#
A[27:17]
CSn#
BHE#
GPO
Decoder
WE0#
WE#
TFT
Bias Power
BS#
VDD
Display