Epson S1D13706 - Table 4-3: Host Interface Pin Descriptions; Host Interface

Page 22
Epson Research and Development
Vancouver Design Center
S1D13706 Hardware Functional Specification
X31B-A-001-08 Issue Date: 01/11/13
4.4 Pin Descriptions
Key:
a
LVTTL is Low Voltage TTL (see Section 5, “D.C. Characteristics” on page 32).
4.4.1 Host Interface
I = Input
O=Output
IO = Bi-Directional (Input/Output)
P=Power pin
LIS = LVTTL
a
Schmitt input
LI = LVTTL input
LB2A = LVTTL IO buffer (6mA/-6mA@3.3V)
LB3P = Low noise LVTTL IO buffer (12mA/-12mA@3.3V)
LO3 = Low noise LVTTL Output buffer (12mA/-12mA@3.3V)
LB3M = Low noise LVTTL IO buffer with input mask (12mA/-12mA@3.3V)
T1 = Test mode control input with pull-down resistor (typical value of 50
Ω
at 3.3V)
Hi-Z = High Impedance
Table 4-3: Host Interface Pin Descriptions
Pin Name Type Pin # Cell
IO
Voltage
RESET#
State
Description
AB0 I 5 LIS HIOVDD 0
This input pin has multiple functions.
• For Generic #1, this pin is not used and should be connected
to VSS.
• For Generic #2, this pin inputs system address bit 0 (A0).
• For SH-3/SH-4, this pin is not used and should be connected
to VSS.
• For MC68K #1, this pin inputs the lower data strobe (LDS#).
• For MC68K #2, this pin inputs system address bit 0 (A0).
• For REDCAP2, this pin is not used and should be connected
to VSS.
• For DragonBall, this pin is not used and should be connected
to VSS.
See Table 4-9: “Host Bus Interface Pin Mapping,” on page 30 for
summary.
AB[16:1] I
87-99,
2-4
LI HIOVDD 0 System address bus bits 16-1.