Epson S1D13706 - 5 GCP Data Signal; GCP Data Structure

Epson Research and Development
Page 19
Vancouver Design Center
Connecting to the Epson D-TFD Panels S1D13706
Issue Date: 01/02/23 X31B-G-012-03
5 GCP Data Signal
The D-TFD panel uses a 256-bit bit chain to control the pixel/FPSHIFT (XSCL) positions
relative to the falling edge of the GPIO4 (RES) signal. A one in each bit indicates the
presence of a GCP pulse at that pixel/XSCL position. A zero indicates the absence of a GCP
pulse. For D-TFD AC Timing required by the S1D13706, see the S1D13706 Hardware
Functional Specification, document number X31B-A-001-xx.
5.1 GCP Data Structure
The S1D13706 uses two registers to program the GCP Data:
• D-TFD GCP Index Register (REG[28h]
• D-TFD GCP Data Register (REG[2Ch])
The 256-bit GCP data is organized into 32 8-bit data registers, each addressable by the D-
TFD GCP Index register (REG[28h]).
Figure 5-1: GCP Data
b7
b0
GCP data register window
GCP index 01h
b7
b0
GCP data register window
GCP index 00h
b7
b0
GCP data register window
GCP index 1Fh
01 2
78
256
GCP bit chain
0
11 10
0
...
...
...
...
b6 b5
GCP
falling edge
of RES