Epson S1D13706 - Table 6-1: Clock Input Requirements for CLKI When CLKI to BCLK Divide > 1; Figure 6-1: Clock Input Requirements; A.C. Characteristics; Clock Timing

Epson Research and Development
Page 33
Vancouver Design Center
Hardware Functional Specification S1D13706
Issue Date: 01/11/13 X31B-A-001-08
6 A.C. Characteristics
Conditions: HIO V
DD
= 2.0V ± 10% and HIO V
DD
= 3.3V ± 10%
NIO V
DD
= 3.3V ± 10%
T
A
= -40
°
C to 85
°
C
T
rise
and T
fall
for all inputs must be < 5 nsec (10% ~ 90%)
C
L
= 50pF (Bus/MPU Interface)
C
L
= 0pF (LCD Panel Interface)
6.1 Clock Timing
6.1.1 Input Clocks
Figure 6-1: Clock Input Requirements
Note
Maximum internal requirements for clocks derived from CLKI must be considered
when determining the frequency of CLKI. See Section 6.1.2, “Internal Clocks” on page
35 for internal clock requirements.
Table 6-1: Clock Input Requirements for CLKI when CLKI to BCLK divide > 1
Symbol Parameter
2.0V 3.3V
Units
Min Max Min Max
f
OSC
Input Clock Frequency (CLKI) 40 100 MHz
T
OSC
Input Clock period (CLKI) 1/f
OSC
1/f
OSC
ns
t
PWH
Input Clock Pulse Width High (CLKI) 4.5 4.5 ns
t
PWL
Input Clock Pulse Width Low (CLKI) 4.5 4.5 ns
t
f
Input Clock Fall Time (10% - 90%) 5 5 ns
t
r
Input Clock Rise Time (10% - 90%) 5 5 ns
t
PWL
t
PWH
t
f
Clock Input Waveform
t
r
T
OSC
V
IH
V
IL
10%
90%