Epson S1D13706 - 4 Power-On;Off Sequence

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Epson Research and Development
Vancouver Design Center
S1D13706 Connecting to the Epson D-TFD Panels
X31B-G-012-03 Issue Date: 01/02/23
4 Power-On/Off Sequence
The D-TFD panel requires a specific sequence to power-on/off. For further information on
power sequencing the D-TFD panel, see the specification for each specific panel.
Figure 4-1: D-TFD Power-On/Off Sequence Timing
1. t1 and t 4 are controlled by software and must be determined from the timing requirements of the panel
connected.
Table 4-1: D-TFD Power-On/Off Sequence Timing
Symbol Parameter Min Max Units
t1
LCD power active to LCD signals active
Note 1
t2
Power Save Mode Enable bit low to LCD signals active
020ns
t3
Power Save Mode Enable bit high to LCD signals low
20 ns
t4
LCD signals low to LCD power inactive
Note 1
t5
LCD signals active to GPIO5 active
2FRAME
t6
GPIO5 Pin IO Status high to GPIO5 active
20 ns
t7
GPIO5 Pin IO Status low to GPIO5 inactive
20 ns
t8
GPIO5 inactive to LCD signals low
3FRAME
*It is recommended that LCD power be controlled using the general output pin GPO.
**The LCD power-off sequence is activated by programming the Power Save Mode Enable bit (REG[A0h] bit 0) to 1.
***LCD Signals include: FPDAT[17:0], FPSHIFT, FPLINE, FPFRAME, DRDY, GPIO6, and GPIO[4:0].
LCD Signals***
GPO*
t1
Power Save
(REG[A0h] bit 0)
Mode Enable**
t3
Active
t2
t8
t4
GPIO5 Pin IO
GPIO5 (DD_P1)
t6
t7
t5
Active
(REG[ACh] bit 5)
Status/Control