Epson S1D13706 - 3 S1 D13706 Host Bus Interface; Host Bus Interface Pin Mapping

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Epson Research and Development
Vancouver Design Center
S1D13706 Interfacing to the Toshiba MIPS TMPR3905/3912 Microprocessors
X31B-G-002-02 Issue Date: 01/02/23
3 S1D13706 Host Bus Interface
The S1D13706 directly supports multiple processors. The S1D13706 implements a 16-bit
Generic #2 Host Bus Interface which is most suitable for connection to the Toshiba
TMPR3905/12 microprocessor.
The Generic #2 Host Bus Interface is selected by the S1D13706 on the rising edge of
RESET#. After releasing reset the bus interface signals assume their selected configuration.
For details on the S1D13706 configuration, see Section 4.2, “S1D13706 Hardware Config-
uration” on page 14.
3.1 Host Bus Interface Pin Mapping
The following table shows the functions of each Host Bus Interface signal.
Table 3-1: Host Bus Interface Pin Mapping
S1D13706
Pin Names
Toshiba TMPR3905/12
AB[16:0] External Decode
DB[15:8] D[23:16]
DB[7:0] D[31:24]
WE1# External Decode
CS# External Decode
M/R# External Decode
CLKI DCLKOUT
BS# connect to HIO V
DD
RD/WR# connect to HIO V
DD
RD# CARDIORD*
WE0# CARDIOWR*
WAIT# CARD1WAIT*
RESET# system RESET