Epson S1D13706 - Page 421

Epson Research and Development
Page 9
Vancouver Design Center
Interfacing to the Toshiba MIPS TMPR3905/3912 Microprocessors S1D13706
Issue Date: 01/02/23 X31B-G-002-02
Figure 2-1: “Toshiba 3905/12 PC Card Memory/Attribute Cycle,” illustrates a typical
memory/attribute cycle on the Toshiba 3905/12 PC Card bus.
Figure 2-1: Toshiba 3905/12 PC Card Memory/Attribute Cycle
Figure 2-2: “Toshiba 3905/12 PC Card IO Cycle,” illustrates a typical IO cycle on the
Toshiba 3905/12 PC Card bus.
Figure 2-2: Toshiba 3905/12 PC Card IO Cycle
A[25:0]
CARD1CSL*
RD*
CARD1WAIT*
D[31:16]
CARDREG*
CARD1CSH*
WE*
ALE
A[25:0]
CARD1CSL*
CARDIORD*
CARD1WAIT*
D[31:16]
CARDREG*
CARD1CSH*
CARDIOWR*
ALE