Epson S1D13706 - Table 6-12: Motorola Dragonball Interface with DTACK Timing

Epson Research and Development
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Hardware Functional Specification S1D13706
Issue Date: 01/11/13 X31B-A-001-08
1. t12 is the delay from when data is placed on the bus until the data is latched into the write buffer.
Table 6-12: Motorola DragonBall Interface with DTACK Timing
Symbol Parameter
MC68EZ328 MC68VZ328
Unit2.0V 3.3V 2.0V 3.3V
Min Max Min Max Min Max Min Max
f
CLKO
Bus Clock frequency 16 16 20 33 MHz
T
CLKO
Bus Clock period
1/f
CLKO
1/f
CLKO
1/f
CLKO
1/f
CLKO
ns
t1 Clock pulse width high 28.1 28.1 22.5 13.5 ns
t2 Clock pulse width low 28.1 28.1 22.5 13.5 ns
t3
A[16:1] setup 1st CLKO when CSX
= 0 and either
UWE
/LWE or OE = 0
0000 ns
t4 A[16:1] hold from CSX rising edge 0000 ns
t5a CSX asserted for MCLK = BCLK 8888T
CLKO
t5b CSX asserted for MCLK = BCLK
÷
2 11111111T
CLKO
t5c CSX asserted for MCLK = BCLK
÷
3 13131313T
CLKO
t5d CSX asserted for MCLK = BCLK
÷
4 17171717T
CLKO
t6 CSX setup to CLKO rising edge 0000 ns
t7 CSX rising edge to CLKO rising edge 0000 ns
t8 UWE/LWE falling edge to CLKO rising edge1010 ns
t9 UWE
/LWE rising edge to CSX rising edge0000 ns
t10 OE falling edge to CLKO rising edge 1111 ns
t11 OE hold from CSX rising edge 0000 ns
t12
D[15:0] setup to 3rd CLKO when CSX
,
UWE
/LWE asserted (write cycle) (see note 1)
1010 ns
t13 D[15:0] in hold from CSX rising edge (write cycle)0000 ns
t14 Falling edge of OE
to D[15:0] driven (read cycle)430315430315 ns
t15
CLKO rising edge to D[15:0] output Hi-Z
(read cycle)
421212421212 ns
t16 CSX
falling edge to DTACK driven high 320313320313 ns
t17 DTACK falling edge to D[15:0] valid (read cycle)0202ns
t18 CSX high to DTACK high 534316534316 ns
t19 CLKO rising edge to D
TACK Hi-Z 5401654016 ns