Epson Research and Development
Page 23
Vancouver Design Center
Hardware Functional Specification S1D13706
Issue Date: 01/11/13 X31B-A-001-08
DB[15:0] IO
18-24,
27-35
LB2A HIOVDD Hi-Z
Input data from the system data bus.
• For Generic #1, these pins are connected to D[15:0].
• For Generic #2, these pins are connected to D[15:0].
• For SH-3/SH-4, these pins are connected to D[15:0].
• For MC68K #1, these pins are connected to D[15:0].
• For MC68K #2, these pins are connected to D[31:16] for a 32-
bit device (e.g. MC68030) or D[15:0] for a 16-bit device (e.g.
MC68340).
• For REDCAP2, these pins are connected to D[15:0].
• For DragonBall, these pins are connected to D[15:0].
See Table 4-9: “Host Bus Interface Pin Mapping,” on page 30
for
summary.
WE0# I 10 LIS HIOVDD 1
This input pin has multiple functions.
• For Generic #1, this pin inputs the write enable signal for the
lower data byte (WE0#).
• For Generic #2, this pin inputs the write enable signal (WE#)
• For SH-3/SH-4, this pin inputs the write enable signal for data
byte 0 (WE0#).
• For MC68K #1, this pin must be tied to HIO V
DD
• For MC68K #2, this pin inputs the bus size bit 0 (SIZ0).
• For REDCAP2, this pin inputs the byte enable signal for the
D[7:0] data byte (EB1).
• For DragonBall, this pin inputs the byte enable signal for the
D[7:0] data byte (LWE
).
See Table 4-9: “Host Bus Interface Pin Mapping,” on page 30
for
summary.
WE1# I 11 LIS HIOVDD 1
This input pin has multiple functions.
• For Generic #1, this pin inputs the write enable signal for the
upper data byte (WE1#).
• For Generic #2, this pin inputs the byte enable signal for the
high data byte (BHE#).
• For SH-3/SH-4, this pin inputs the write enable signal for data
byte 1 (WE1#).
• For MC68K #1, this pin inputs the upper data strobe (UDS#).
• For MC68K #2, this pin inputs the data strobe (DS#).
• For REDCAP2, this pin inputs the byte enable signal for the
D[15:8] data byte (EB0
).
• For DragonBall, this pin inputs the byte enable signal for the
D[15:8] data byte (UWE
).
See Table 4-9: “Host Bus Interface Pin Mapping,” on page 30
for
summary.
CS# I 6 LI HIOVDD 1
Chip select input. See Table 4-9: “Host Bus Interface Pin Mapping,”
on page 30
for summary.
M/R# I 7 LIS HIOVDD 0
This input pin is used to select between the display buffer and
register address spaces of the S1D13706. M/R# is set high to
access the display buffer and low to access the registers. See
Table 4-9: “Host Bus Interface Pin Mapping,” on page 30
for
summary.
Table 4-3: Host Interface Pin Descriptions
Pin Name Type Pin # Cell
IO
Voltage
RESET#
State
Description
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