Epson S1D13706 - Page 30

Page 24
Epson Research and Development
Vancouver Design Center
S1D13706 Hardware Functional Specification
X31B-A-001-08 Issue Date: 01/11/13
BS# I 8 LIS HIOVDD 1
This input pin has multiple functions.
• For Generic #1, this pin must be tied to HIO V
DD
.
• For Generic #2, this pin must be tied to HIO V
DD
.
• For SH-3/SH-4, this pin inputs the bus start signal (BS#).
• For MC68K #1, this pin inputs the address strobe (AS#).
• For MC68K #2, this pin inputs the address strobe (AS#).
• For REDCAP2, this pin must be tied to HIO V
DD
.
• For DragonBall, this pin must be tied to HIO V
DD
.
See Table 4-9: “Host Bus Interface Pin Mapping,” on page 30 for
summary.
RD/WR# I 12 LIS HIOVDD 1
This input pin has multiple functions.
• For Generic #1, this pin inputs the read command for the
upper data byte (RD1#).
• For Generic #2, this pin must be tied to HIO V
DD
.
• For SH-3/SH-4, this pin inputs the RD/WR# signal. The
S1D13706 needs this signal for early decode of the bus cycle.
• For MC68K #1, this pin inputs the R/W# signal.
• For MC68K #2, this pin inputs the R/W# signal.
• For REDCAP2, this pin inputs the R/W
signal.
• For DragonBall, this pin must be tied to HIO V
DD
.
See Table 4-9: “Host Bus Interface Pin Mapping,” on page 30 for
summary.
RD# I 9 LIS HIOVDD 1
This input pin has multiple functions.
• For Generic #1, this pin inputs the read command for the lower
data byte (RD0#).
• For Generic #2, this pin inputs the read command (RD#).
• For SH-3/SH-4, this pin inputs the read signal (RD#).
• For MC68K #1, this pin must be tied to HIO V
DD
.
• For MC68K #2, this pin inputs the bus size bit 1 (SIZ1).
• For REDCAP2, this pin inputs the output enable (OE).
• For DragonBall, this pin inputs the output enable (OE
).
See Table 4-9: “Host Bus Interface Pin Mapping,” on page 30 for
summary.
Table 4-3: Host Interface Pin Descriptions
Pin Name Type Pin # Cell
IO
Voltage
RESET#
State
Description