Epson Research and Development
Page 9
Vancouver Design Center
Interfacing to the Motorola MC68030 Microprocessor S1D13706
Issue Date: 01/02/23 X31B-G-013-02
signals the start of a bus cycle by indicating a valid address has been placed on the bus. DS
(the data strobe) is used as a condition for valid data on the data bus. SIZ selects the active
portions of the data bus. R/W
indicates a read or write operation.
Synchronous bus cycles operate much like asynchronous cycles except only 32-bit port
sizes are allowed. In this mode the DSACK
signals are not required. Wait states are inserted
with the synchronous signal (STERM
) which signals that the data is to be latched on the
next clock when asserted.
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