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Epson Research and Development
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S1D13706 Hardware Functional Specification
X31B-A-001-08 Issue Date: 01/11/13
bits 9-0 FPFRAME Pulse Start Position Bits [9:0]
These bits specify the start position of the vertical sync signal, in 1 line resolution.
For passive panels, these bits must be set to 00h.
For TFT/HR-TFT/D-TFD panels, VDPS is calculated using the following formula:
VPS = (REG[27h] bits 1-0, REG[26h] bits 7-0)
Note
For panel AC timing and timing parameter definitions, see Section 6.4, “Display Inter-
face” on page 56.
bits 4-0 D-TFD GCP Index Bits [4:0]
For D-TFD panels only.
These bits form the index that points to 32 8-bit GCP data regis-
ters.
bits 7-0 D-TFD GCP Data Bits [7:0]
For D-TFD panel only.
This register stores the data to be written to the GCP data bits and
is controlled by the D-TFD GCP Index register (REG[28h]). For further information on
the use of this register, see Connecting to the Epson D-TFD Panels, document number
X31B-G-012-xx.
Note
The Panel Type bits (REG[10h] bits 1:0) must be set to 11 (D-TFD) for the GCP Data
bits to have any hardware effect.
FPFRAME Pulse Start Position Register 0
REG[26h] Read/Write
FPFRAME Pulse Start Position Bits 7-0
76543210
FPFRAME Pulse Start Position Register 1
REG[27h] Read/Write
n/a
FPFRAME Pulse Start
Position Bits 9-8
7 6 5 4 3 210
D-TFD GCP Index Register
REG[28h] Read/Write
n/a D-TFD GCP Index Bits 4-0
7 6 543210
D-TFD GCP Data Register
REG[2Ch] Read/Write
D-TFD GCP Data Bits 7-0
76543210
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