Epson S1D13706 - Page 121

Epson Research and Development
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Vancouver Design Center
Hardware Functional Specification S1D13706
Issue Date: 01/11/13 X31B-A-001-08
8.3.6 Picture-in-Picture Plus (PIP
+
) Registers
bits 16-0 PIP
+
Window Display Start Address Bits [16:0]
These bits form the 17-bit address for the starting double-word of the PIP
+
window.
Note that this is a double-word (32-bit) address.
An entry of 00000h into these registers
represents the first double-word of display memory, an entry of 00001h represents the sec-
ond double-word of the display memory, and so on.
Note
These bits have no effect unless the PIP
+
Window Enable bit is set to 1 (REG[71h] bit
4).
bits 9-0 PIP
+
Window Line Address Offset Bits [9:0]
These bits are the LCD display’s 10-bit address offset from the starting double-word of
line “n” to the starting double-word of line “n + 1” for the PIP
+
window.
Note that this is
a 32-bit address increment.
Note
These bits have no effect unless the PIP
+
Window Enable bit is set to 1 (REG[71h] bit
4).
PIP
+
Window Display Start Address Register 0
REG[7C] Read/Write
PIP
+
Window Display Start Address Bits 7-0
76543210
PIP
+
Window Display Start Address Register 1
REG[7Dh] Read/Write
PIP
+
Window Display Start Address Bits 15-8
76543210
PIP
+
Window Display Start Address Register 2
REG[7Eh] Read/Write
n/a
PIP
+
Window
Display Start
Address
Bit 16
7 6 5 4 3 2 10
PIP
+
Window Line Address Offset Register 0
REG[80h] Read/Write
PIP
+
Window Line Address Offset Bits 7-0
76543210
PIP
+
Window Line Address Offset Register 1
REG[81h] Read/Write
n/a
PIP
+
Window Line Address
Offset Bits 9-8
7 6 5 4 3 210