Epson Research and Development
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Vancouver Design Center
Hardware Functional Specification S1D13706
Issue Date: 01/11/13 X31B-A-001-08
bit 0 GPIO0 Pin IO Status
When neither a D-TFD panel or a HR-TFT are selected (REG[10h] bits 1:0) and GPIO0 is
configured as an output, writing a 1 to this bit drives GPIO0 high and writing a 0 to this bit
drives GPIO0 low.
When neither a D-TFD panel or a HR-TFT are selected (REG[10h] bits 1:0) and GPIO0 is
configured as an input, a read from this bit returns the status of GPIO0.
When a D-TFD panel is enabled (REG[10h] bits 1:0 = 11), GPIO0 outputs the XINH sig-
nal automatically and writing to this bit has no effect.
When a HR-TFT panel is enabled (REG[10h] bits 1:0 = 10), GPIO0 outputs the PS signal
automatically and writing to this bit has no effect.
bit 7 GPO Control
This bit controls the General Purpose Output pin.
Writing a 0 to this bit drives GPO to low.
Writing a 1 to this bit drives GPO to high.
Note
Many implementations use the GPO pin to control the LCD bias power (see Section 6.3,
“LCD Power Sequencing” on page 54).
General Purpose IO Pins Status/Control Register 1
REG[ADh] Read/Write
GPO Control n/a
7 6 5 4 3 2 1 0
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