Epson S1D13706 - Page 147

Epson Research and Development
Page 141
Vancouver Design Center
Hardware Functional Specification S1D13706
Issue Date: 01/11/13 X31B-A-001-08
Line Address Offset
The Main Window Line Address Offset registers (REG[78h], REG[79h]) is based on the
display width and programmed using the following formula.
Main Window Line Address Offset bits 9:0
= display width in pixels
÷
(32
÷
bpp)
= 480 pixels
÷
32
÷
8 bpp
= 120 (78h)
12.4 270° SwivelView™
270
°
SwivelView™ requires the Memory Clock (MCLK) to be at least 1.25 times the
frequency of the Pixel Clock (PCLK), i.e. MCLK
≥
1.25PCLK.
The following figure shows how the programmer sees a 320x480 portrait image and how
the image is being displayed. The application image is written to the S1D13706 in the
following sense: A–B–C–D. The display is refreshed by the S1D13706 in the following
sense: C-A-D-B.
Figure 12-3: Relationship Between The Screen Image and the Image Refreshed in 270
°
SwivelView.
image seen by programmer
= image in display buffer
480
SwivelView
window
480
320
AB
C
D
D
C
B
A
320
SwivelView
window
image refreshed by S1D13706
physical memory
display start address
(panel origin)
start address