Epson S1D13706 - Page 171

Epson Research and Development
Page 11
Vancouver Design Center
Programming Notes and Examples S1D13706
Issue Date: 01/02/23 X31B-G-003-03
The following table represents the sequence and values written to the S1D13706 registers
to control a configuration with these specifications.
• 320x240 color single passive LCD @ 70Hz.
• 8-bit data interface, format 2.
• 8 bit-per-pixel (bpp) color depth - 256 colors.
• 50MHz input clock for CLKI.
• MCLK = BCLK = CLKI = 50MHz.
• PCLK = CLKI
÷
8 = 6.25MHz.
Note
On the S5U13706B00C evaluation board, CNF[7:6] must be set to 00.
Table 2-1: Example Register Values
Register
Value
(Hex)
Value
(Binary)
Description Notes
Clock Configuration (MCLK, BCLK, PCLK)
04h 00 0000 0000 Sets BCLK to MCLK divide to 1:1
05h 43 0100 0011 Sets PCLK = (PCLK source
÷
8) and the PCLK source = CLKI2
Panel Setting Configuration
10h D0 1101 0000
Selects the following:
• panel data format = 2
• color/mono panel = color
• panel data width = 8-bit
• active panel resolution = don’t care
• panel type = STN
11h 00 0000 0000 MOD rate = don’t care
12h 2B 0010 1011 Sets the horizontal total
14h 27 0010 0111 Sets the horizontal display period
16h
17h
00
00
0000 0000
0000 0000
Sets the horizontal display period start position
18h
19h
FA
00
1111 1010
0000 0000
Sets the vertical total
1Ch
1Dh
EF
00
1110 1111
0000 0000
Sets the vertical display period
1Eh
1Fh
00
00
0000 0000
0000 0000
Sets the vertical display period start position
20h 87 1000 0111 Sets the FPLINE pulse polarity and FPLINE pulse width
22h
23h
00
00
0000 0000
0000 0000
Sets the FPLINE pulse start position
24h 80 1000 0000 Sets the FPFRAME pulse polarity and FPFRAME pulse width
26h
27h
01
00
0000 0001
0000 0000
Sets the FPFRAME pulse start position